Front stage process of a fully depleted silicon-on-insulator...

Details Front stage process of a fully depleted silicon-on-insulator... Front stage process of a fully depleted silicon-on-insulator...

2002-04-09

2003-01-21

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S166000, C438S164000

Reexamination Certificate

active

06509218

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a front stage process of an active device within an integrated circuit, and the structure thereof. More particularly, the present invention relates to the front stage process of a fully depleted silicon-on-insulator (SOI) device, and the structure thereof.
2. Description of the Related Art
Silicon-on-insulator (SOI) devices are semiconductor devices of the new era. The SOI substrate structure comprises an insulator and a crystalline silicon layer above the insulator. The device is fabricated above the crystalline silicon layer. Compared to Metal Oxide Semiconductors (MOS) fabricated on bulk silicon substrates, SOI metal oxide semiconductors (MOS) possess the following advantages:
1.) The electrical consumption of SOI-MOS is much lower because the underside of the crystalline silicon layer has an insulation layer that can prevent current leakage.
2. The threshold voltage (Vt) of the SOI-MOS is much lower because the crystalline silicon layer is very thin.
3. The performance of the SOI-MOS is much higher because the parasitic capacitance of the SOI-MOS source/drain region is very small.
SOI-MOS are differentiated based on their operating state. The two kinds include partially depleted mode and fully depleted mode SOI-MOS. The special characteristic of fully depleted SOI-MOS is that the crystalline silicon layer above the insulation layer is very thin. Consequently, the entire area, from the bottom of the channel region to the insulation layer, becomes a depleted region when the SOI-MOS operates.
Compared to partially depleted SOI-MOS, the electrical consumption and threshold voltage of fully depleted SOI-MOS are both much lower. Moreover, the performance is much higher.
The fabrication steps of the conventional SOI-MOS are summarized below. As shown in
FIG. 1A
, a silicon-on-insulation (SOI) substrate
100
is provided, wherein the insulation layer comprises a silicon oxide layer
110
and a crystalline silicon layer
120
overlying the silicon oxide layer
110
. One method for fabricating the SOI substrate
100
includes implanting oxide ions into a silicon substrate and performing a thermal step to cause the ions and the oxide to react, resulting in the formation of silicon the oxide layer
110
. The silicon material on the surface forms the crystalline silicon layer
120
. A silicon oxide isolation layer
130
connected to the silicon oxide layer
110
is formed in crystalline silicon layer
120
, to define PMOS active region
132
and NMOS active region
134
.
As shown in
FIG. 1B
, NMOS active region
134
is covered with a photoresist layer
136
. Using the photoresist layer
136
as a mask, n-type doped ions
138
are implanted into crystalline silicon layer
120
within PMOS active region
132
, converting the crystalline silicon layer
120
within PMOS active region
132
into an n-type doped well
140
.
As shown in
FIG. 1C
, the photoresist layer
136
is removed. The PMOS active region
132
is then covered by a photoresist layer
146
. Using the photoresist layer
146
as a mask, p-type ions
148
are implanted into the crystalline silicon layer
120
within NMOS active region
134
, converting the crystalline silicon layer
120
in the NMOS active region
134
into a p-type doped well
150
.
As shown in
FIG. 1D
, the photoresist layer
146
is removed. A gate oxide layer
153
is then formed above the n-type doped well
140
(p-type doped well
150
). Gates
154
a
and
154
b
are then formed above gate oxide layer
153
. A p-type lightly doped drain
160
is formed in n-type doped well
140
on opposite sides of gate
154
a.
Similarly, an n-type lightly doped drain
170
is formed in p-type doped well
150
on opposites sides of gate
154
b.
Spacers
173
a
and
173
b
are then formed on the sidewalls of gates
154
a
and
154
b,
respectively. A p-type source/drain region
180
is then formed in the n-type doped well
140
beside the spacer
173
a.
Similarly, an n-type source/drain region
190
is formed in the p-type doped well
150
on an exterior side of the spacer
173
b.
This step completes the fabrication of a p-type (n-type) fully depleted SOI device
192
(
194
).
FIG. 2
shows the ideal doping distribution within channel region
196
(
198
) of the p-type (n-type) SOI device achieved by the conventional fabrication method. In the channel region
196
(
198
), shown above the dotted line, the doping concentration of the area near the gate oxide layer
153
is much lower, in order to lower the threshold voltage. The doping concentration of the central portion of the channel region is the highest, to enhance the anti-punch through effect. The doping distribution of the channel region
196
(
198
) is referred to as “delta doping”.
As the dimensions of electronic devices grow increasingly smaller, the thickness of crystalline silicon layer
120
above silicon oxide layer
110
becomes thinner. In advanced fabrication processes, the thickness of the crystalline silicon layer
120
can fall between 200 Å and 500 Å, causing the following disadvantages of the p-type (n-type) fully depleted SOI device:
1. The crystalline silicon layer
120
is very thin. Thus, when ions are implanted into the crystalline silicon layer
120
, to form the n-type and the p-type wells
140
and
150
, the doping distribution is very difficult to control. Consequently, the threshold voltage and source/drain resistivity are unstable. Moreover, the channel region
196
(
198
) does not easily attain the ideal delta doping distribution as shown in FIG.
2
.
2. Because the crystalline silicon layer
120
is extremely thin, the p-type lightly doped drain
160
and the n-type lightly doped drain
170
are difficult to form.
3. Because crystalline silicon layer
120
is extremely thin, the self-aligned silicide, formed above the p-type (n-type) source/drain regions
180
(
190
) in a subsequent step, will consume a large portion of silicon in the crystalline silicon layer
120
, which compromises the junction integrity of the p-type (n-type) source/drain regions
180
(
190
).
4. When high temperature is applied to the oxide ions in the SOI substrate fabrication method discussed above, the distribution range of implanted oxide ions is very wide (relative to the thickness of crystalline silicon layer
120
). This causes the crystalline silicon layer
120
to contain a rather large amount of oxide atoms. As a consequence, the quality of the self-aligned silicide formed above the p-type (n-type) source/drain regions
180
(
190
) is lowered.
SUMMARY OF THE INVENTION
The invention provides a front stage process for a fully depleted SOI having the following steps: an SOI substrate with an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer connected to the insulation layer is formed, to define a first-type MOS active region. The first-type is either p-type or n-type. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is then selectively formed above the crystalline silicon layer in the first-type MOS active region. This second-type doped epitaxial silicon layer is doped in-situ. An undoped epitaxial silicon layer is then selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
The invention provides a fully depleted SOI device front stage process used in the fabrication process for a co-existing PMOS and NMOS. The steps of the front stage process are as follows: an SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer are provided. An isolation layer connected to the insulation layer is formed in the crystalline silicon layer, in order to define a first-type MOS active region and a second-type MOS active region. A first epitaxial suppressing layer is formed over the crystalline silicon layer in the second-type MOS act

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