LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...,Having insulated gate

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Multi-layer spacer technology for flash EEPROM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-layer spacer with inhibited recess/undercut and method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-layer tunneling device with a graded stoichiometry...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-layered gate for a CMOS imager

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-level (4 state/2-bit) stacked gate flash memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-level dram trench store utilizing two capacitors and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-level flash memory using triple well process and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-level gate SONOS flash memory device with high voltage...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-level memory cell and fabricating method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-level, split-gate, flash memory cell and method of manufac

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-metal-oxide high-K gate dielectrics

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-operational mode transistor with multiple-channel...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-state memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-state non-volatile integrated circuit memory systems...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-state non-volatile integrated circuit memory systems...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-state non-volatile integrated circuit memory systems...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Multi-state NROM device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-state NROM device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-step annealing process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Multi-step chemical mechanical polishing of a gate area in a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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