Multi-layer spacer technology for flash EEPROM
Multi-layer spacer with inhibited recess/undercut and method...
Multi-layer tunneling device with a graded stoichiometry...
Multi-layered gate for a CMOS imager
Multi-level (4 state/2-bit) stacked gate flash memory cell
Multi-level dram trench store utilizing two capacitors and...
Multi-level flash memory using triple well process and...
Multi-level gate SONOS flash memory device with high voltage...
Multi-level memory cell and fabricating method thereof
Multi-level, split-gate, flash memory cell and method of manufac
Multi-metal-oxide high-K gate dielectrics
Multi-operational mode transistor with multiple-channel...
Multi-state memory cell
Multi-state non-volatile integrated circuit memory systems...
Multi-state non-volatile integrated circuit memory systems...
Multi-state non-volatile integrated circuit memory systems...
Multi-state NROM device
Multi-state NROM device
Multi-step annealing process
Multi-step chemical mechanical polishing of a gate area in a...