Multi-step annealing process

Details Multi-step annealing process Multi-step annealing process

2006-03-31

2010-10-12

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S663000

Reexamination Certificate

active

07811892

ABSTRACT:
A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

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“A High Density 0.10μm CMOS Technology Using Low K Dielectric and Copper Interconnect” jointly authored by Parihar, et al., Mortorola DigitalDNA Laboratories and AMD Technology Development Group.

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