Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-26
2001-03-27
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S261000, C438S593000, C438S595000, C438S596000
Reexamination Certificate
active
06207507
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor flash memory, and more particularly, to a multi-level flash memory using a triple well process.
BACKGROUND OF THE INVENTION
Flash memory is classified as non-volatile memory because a memory cell in the flash memory can retain the data stored in the memory cell without periodic refreshing. Most prior art flash memory can store a single bit in a memory cell. In other words, the memory cell can either store a “one” or a “zero”. Multi-level flash memory can store two bits per memory cell.
Multi-level flash memory is becoming more popular because of its advantages. In particular, multi-level flash memory lowers the cost per bit for non-volatile memory storage. Further, multi-level flash memory also allows for higher density memories because each memory cell can store two or more bits of data.
Prior art multi-level flash memory has suffered from the problem of difficulty in controlling the data level in the memory cell. Complex electrical circuits are needed to control the program and erase data level of these prior art memory cells. The most difficult aspect is that the data level will shift after cycling tests. What is needed is a multi-level flash memory cell design that is easily written to and read from and is easy to manufacture.
SUMMARY OF THE INVENTION
The present invention provides a new memory cell structure that is easily programmable. A multi-level flash memory cell formed in a semiconductor substrate is disclosed. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.
REFERENCES:
patent: 5284784 (1994-02-01), Manley
patent: 5379255 (1995-01-01), Shah
patent: 5478767 (1995-12-01), Hong
patent: 5614747 (1997-03-01), Ahn et al.
patent: 5747370 (1998-05-01), Lee
patent: 5760435 (1998-06-01), Pan
patent: 6117731 (2000-09-01), Wu
Blakely , Sokoloff, Taylor & Zafman LLP
Lee Eddie C.
Richards N. Drew
Taiwan Semiconductor Manufacturing Corp.
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