Multi-level gate SONOS flash memory device with high voltage...

Details Multi-level gate SONOS flash memory device with high voltage... Multi-level gate SONOS flash memory device with high voltage...

2006-03-21

2006-03-21

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S261000

Reexamination Certificate

active

07015101

ABSTRACT:
A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

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patent: 6383871 (2002-05-01), Nobel et al.
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patent: 6465303 (2002-10-01), Ramsbey et al.
patent: 6853587 (2005-02-01), Forbes
patent: 2005/0079674 (2005-04-01), Zheng et al.

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