Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-17
2008-11-04
Dang, Trung (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C257SE21626
Reexamination Certificate
active
07446007
ABSTRACT:
A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
REFERENCES:
patent: 5760451 (1998-06-01), Yu
patent: 5783479 (1998-07-01), Lin et al.
patent: 6512266 (2003-01-01), Deshpande et al.
patent: 6541351 (2003-04-01), Bartlau et al.
patent: 2005/0003589 (2005-01-01), Doris et al.
patent: 2005/0116289 (2005-06-01), Boyd et al.
patent: 2005/0118826 (2005-06-01), Boyd et al.
patent: 2005/0184360 (2005-08-01), Ho et al.
patent: 2005/0287823 (2005-12-01), Ramachandran et al.
patent: 2006/0001095 (2006-01-01), Doris et al.
patent: 2006/0017066 (2006-01-01), Geiss et al.
Adkisson James W.
Cantell Marc W.
Elliott James R.
Hart, III James V.
Martin Dale W.
Dang Trung
International Business Machines - Corporation
Sabo, Esq. William D.
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Multi-layer spacer with inhibited recess/undercut and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-layer spacer with inhibited recess/undercut and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer spacer with inhibited recess/undercut and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4027039