Multi-level memory cell and fabricating method thereof

Details Multi-level memory cell and fabricating method thereof Multi-level memory cell and fabricating method thereof

2006-08-29

2006-08-29

Malsawma, Lex H. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07098109

ABSTRACT:
A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.

REFERENCES:
patent: 6706579 (2004-03-01), Kasuya
patent: 2003/0042531 (2003-03-01), Lee et al.

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