Multi-step chemical mechanical polishing of a gate area in a...

Details Multi-step chemical mechanical polishing of a gate area in a... Multi-step chemical mechanical polishing of a gate area in a...

2005-02-15

2005-02-15

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S633000, C438S959000

Reexamination Certificate

active

06855607

ABSTRACT:
A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

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Digh Hisamoto et al.: “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin FET Technologies,” 0-7803-5410-9/99 IEEE, Mar. 2001, 4 pages.
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Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 0-7803-7050-3/01 IEEE, Sep. 1999 4 pages.

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