Multi-layer spacer technology for flash EEPROM

Details Multi-layer spacer technology for flash EEPROM Multi-layer spacer technology for flash EEPROM

1998-02-13

2000-05-30

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438595, H01L 218247

Patent

active

060690429

ABSTRACT:
A method is provided for forming multi-layer spacer GELS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si.sub.3 N.sub.4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMS.

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patent: 5115288 (1992-05-01), Manley
patent: 5364804 (1994-11-01), Ho et al.
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patent: 5573965 (1996-11-01), Chen et al.
patent: 5633184 (1997-05-01), Tamura et al.
patent: 5879993 (1999-03-01), Chien et al.

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