Localized spacer for a multi-gate transistor
Locally confined deep pocket process for ULSI mosfets
Logic circuit and its fabrication method
Logic SOI structure, process and application for vertical...
Long retention time single transistor vertical memory gain cell
Long retention time single transistor vertical memory gain cell
Low and high voltage CMOS devices and process for fabricating sa
Low and high voltage CMOS devices and process for...
Low capacitance ESD protection device
Low capacitance junction-isolation for bulk FinFET technology
Low cost deep sub-micron CMOS process
Low cost fabrication method for high voltage, high drain...
Low cost fabrication of high resistivity resistors
Low cost source drain elevation through poly amorphizing...
Low cost transistors using gate orientation and optimized...
Low cost well process
Low damage doping technique for self-aligned source and drain re
Low defect density process for deep sub-0.18 &mgr;m flash...
Low dielectric constant shallow trench isolation
Low dielectric constant shallow trench isolation