Low cost well process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438218, 438225, 438227, H01L 218238

Patent

active

057598819

ABSTRACT:
The present invention develops a process for forming dual conductive wells in a silicon substrate for an integrated circuit by: forming an oxide layer on the silicon substrate; patterning an oxidation barrier layer on the oxide layer, thereby defining active areas for active devices; introducing first p-type conductive impurities into the silicon substrate thereby forming at least one p-type conductively doped well region; masking over the p-type conductively doped well region; introducing n-type conductive impurities into the silicon substrate thereby forming at least one n-type conductively doped well region; removing the masking; forming oxide regions in areas not covered by the patterned oxidation barrier layer; and forcing the p-type and n-type conductive impurities further into the silicon substrate thereby forming the dual well regions, the well regions having adequate conductive depth to provide for the formation of the active devices.

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Wolf et al, "Silicon Processing for the VLSI Era", vol. II, Lattice Press, 1990, pp. 368-389.
Ghandhi; VLSI Fabrication Principles, John Wiley & Sons, Inc., 1983, pp. 353-354.
Wolf et al., vol. II, Silicon Processing for the VLSI Era, Lattice Press, 1990 pp. 20-28; 419-427; 428-441.

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