Low cost transistors using gate orientation and optimized...

Details Low cost transistors using gate orientation and optimized... Low cost transistors using gate orientation and optimized...

2011-08-09

2011-08-09

Luu, Chuong A (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C257SE27060

Reexamination Certificate

active

07994009

ABSTRACT:
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

REFERENCES:
patent: 5925914 (1999-07-01), Jiang et al.
patent: 5963809 (1999-10-01), Duane et al.

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