Low and high voltage CMOS devices and process for fabricating sa

Details Low and high voltage CMOS devices and process for fabricating sa Low and high voltage CMOS devices and process for fabricating sa

1998-02-12

2000-08-01

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438443, 438450, 438451, 438271, 438298, 438291, 438275, H01L 218249

Patent

active

060965894

ABSTRACT:
CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

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