Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-22
2004-09-14
Lee, Eddie C. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S313000, C438S311000, C438S336000, C438S321000, C438S325000, C438S378000
Reexamination Certificate
active
06790722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of vertical bipolar transistors and more particularly to a method and process of forming vertical bipolar transistors simultaneously with field effect transistors using a damascene process.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology, which is becoming of increasing importance in the field of integrated circuits, deals with the formation of transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. Devices formed on SOI offer many advantages over their bulk counterparts, including: higher performance, absence of latch-up, higher packing density, low voltage applications, etc. SOI technology provides a very high performance regime for complementary metal oxide semiconductor (CMOS) operation due to a unique isolation structure.
It is advantageous in semiconductor manufacturing to simultaneously produce as many different types of devices on a chip as possible. Such simultaneous production reduce the number of steps and the amount of material required to make the chip. This reduces the time and cost of producing semiconductor chips. Therefore, it is desirable to simultaneously form different types of transistors on a single chip.
There is a conventional need to integrate a complementary pair of bipolar devices within the SOI CMOS framework for low voltage, high performance operation, thereby making use of as much of the SOI CMOS advantages as possible. The invention discussed below is directed to a methodology that simultaneously forms field effect transistors (e.g. CMOS transistors) and bipolar transistors using a damascene process to form the CMOS gates and the bipolar emitters.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method of forming an emitter in a vertical bipolar transistor. The emitter forms a patterned mask over the collector layer and fills openings in the mask with emitter material in a damascene process. The substrate includes an insulator layer between a bottom silicon layer and a top silicon layer, and the invention implants a first impurity to form the collector layer in a lower portion of the top silicon layer adjacent the insulator layer, and a second impurity to form the base layer in an upper portion of the top silicon layer.
The emitter material includes a first impurity that is annealed to drive the first impurity into the base to create an emitter diffusion region in the base below each emitter. The substrate also includes a patterned second mask over the bipolar region, the mask includes openings through to the base layer between adjacent ones of the emitters, and the invention implants additional amounts of the second impurity into the base layer through the openings. The invention can also include forming a protective layer over the emitters and implanting additional amounts of the first impurity into the insulator layer to provide a collector contact diffusion region.
The invention also includes a method of simultaneously forming complementary methal oxide semiconductor devices and vertical bipolar transistors on an integrated circuit chip that includes providing a silicon over insulator substrate having a collector layer and a base layer over the collector; forming a polysilicon layer over a CMOS region of the SOI substrate, patterning a mask over the polysilicon layer and a bipolar region of the SOI substrate (the mask include openings over the bipolar region), depositing an emitter material in the openings in a damascene process to form emitters, removing the mask, patterning the polysilicon layer to form gate conductors, and forming sidewall spacers adjacent the emitters and the gate conductors.
The invention also includes a CMOS/vertical bipolar structure, in which the collector, base regions, and emitter regions are vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
REFERENCES:
patent: 4902639 (1990-02-01), Ford
patent: 5087580 (1992-02-01), Eklund
patent: 5279978 (1994-01-01), See et al.
patent: 5352624 (1994-10-01), Miwa et al.
patent: 5356822 (1994-10-01), Lin et al.
patent: 5406113 (1995-04-01), Horie
patent: 5446312 (1995-08-01), Hsieh et al.
patent: 5541120 (1996-07-01), Robinson et al.
patent: 5581101 (1996-12-01), Ning et al.
patent: 5583059 (1996-12-01), Burghartz
patent: 5587599 (1996-12-01), Mahnkopf et al.
patent: H1637 (1997-03-01), Offord et al.
patent: 5646055 (1997-07-01), Tsoi
patent: 5744855 (1998-04-01), Maki et al.
patent: 5849613 (1998-12-01), Peidous
patent: 5851864 (1998-12-01), Ito et al.
patent: 5904536 (1999-05-01), Blair
patent: 6001700 (1999-12-01), Peidous
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6222250 (2001-04-01), Gomi
patent: 6284581 (2001-09-01), Pan et al.
Houghton Russell J.
Mandelman Jack A.
Pricer Wilbur D.
Tonti William R.
Canale Anthony
Gebremariam Samuel A
Lee Eddie C.
McGinn & Gibb PLLC
LandOfFree
Logic SOI structure, process and application for vertical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic SOI structure, process and application for vertical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic SOI structure, process and application for vertical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3224707