Low cost source drain elevation through poly amorphizing...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S655000

Reexamination Certificate

active

07101743

ABSTRACT:
A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.

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Ranade et al., “A novel elevated S.D PMOSFET Formed by Ge-B/Si Intermixing”, IEEE electron device letters, vol. 23, No. 4, Apr. 2002. pp. 218-220.

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