Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-30
2003-04-01
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S529000
Reexamination Certificate
active
06541338
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to high performance microelectronic flash memory cells and to the art of manufacturing high performance microelectronic flash memory cells. Even more specifically, this invention relates to a method of manufacturing high performance microelectronic flash memory cells with low defect density.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory array are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary
1
or
0
, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells in a either a column or a row are connected together and each column or row common source connections are then connected to a common source voltage V
SS
. This arrangement is known as a NOR flash memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the common voltage source V
SS
, which causes hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein which increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 5 volts to the control gate, applying 1 volt to the bitline to which the drain is connected, grounding the common source voltage V
SS
, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. A cell can also be erased by applying a negative voltage on the order of −10 volts to the control gate, applying 5 volts to the source and allowing the drain to float. Another method of erasing is by applying 5V to the P-well and −10V to the control gate while allowing the source/drain to float.
However, as the dimensions of the flash memory array have been aggressively scaled down and the product arrays produced with ultra high density, one important yield factor for deep sub-0.18 &mgr;m high performance non-volatile memory cell is the high defect density from the heavily-damaged source junction due to the high energy source implant.
Therefore, what is needed is a method of providing a low energy source implant and a high energy V
SS
connection implant in such a way that the intrinsic source defect density will be reduced.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of manufacturing flash memory devices having a low energy source implant and a high energy V
SS
connection implant such that the intrinsic source defect density is reduced and the V
SS
resistance is low.
In accordance with an aspect of the invention, a first mask is formed exposing source regions and the exposed source regions are implanted with n dopant ions. The first mask is removed and a second mask is formed exposing regions between adjacent source regions and the exposed regions are implanted with n
+
dopant ions.
The described method thus provides flash memory devices having a low intrinsic source defect density with a low V
SS
resistance.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 6337250 (2002-01-01), Furuhata
patent: 6395592 (2002-05-01), Wu
patent: 2001/0008786 (2001-07-01), Tsukiji
Fastow Richard
He Yue-Song
Wang Zhigang
Advanced Micro Devices , Inc.
Chaudhari Chandra
LandOfFree
Low defect density process for deep sub-0.18 &mgr;m flash... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low defect density process for deep sub-0.18 &mgr;m flash..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low defect density process for deep sub-0.18 &mgr;m flash... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3105367