Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-07-03
1999-11-02
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438559, 438563, 438231, H01L 21336
Patent
active
059769394
ABSTRACT:
A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.
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patent: 4079504 (1978-03-01), Kosa
patent: 4204894 (1980-05-01), Komeda et al.
patent: 5173440 (1992-12-01), Tsunashima et al.
patent: 5234850 (1993-08-01), Liao
patent: 5518945 (1996-05-01), Bracchitta et al.
Bohr Mark T.
Packan Paul A.
Thompson Scott
Intel Corporation
Trinh Michael
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