Low cost deep sub-micron CMOS process

Details Low cost deep sub-micron CMOS process Low cost deep sub-micron CMOS process

1998-08-19

2001-02-06

Mulpupi, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S232000, C438S514000

Reexamination Certificate

active

06184099

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method of fabricating semiconductor integrated circuits, and more specifically to a method of forming proper source/drain junctions and transistor characteristics in a deep sub-micron complementary MOS (CMOS).
BACKGROUND
Current deep sub-micron CMOS processes use four photolithography steps to form proper source/drain (S/D) junctions having lightly doped drain (LDD) junctions, and to produce desired transistor characteristics.
FIG. 1
shows a cross-sectional view of a semiconductor substrate
10
in an intermediate stage of a standard deep sub-micron CMOS process. Substrate
10
is shown with isolation regions
15
, a gate oxide layer
20
on the surface of substrate
10
, and polysilicon gates
25
. A photoresist layer
30
is patterned over a N− well
35
and a masked N− implant is ther performed, creating self-aligned NLDD junctions
40
. A P− implant is also performed creating halo regions
45
. Photoresist layer
30
is then removed and a thermal cycle drives in the N− implant and the P− implant. A second photoresist layer
50
is then patterned over substrate
10
, as shown in
FIG. 2. A
masked P− implant is performed creating self-aligned PLDD junctions
55
.
FIG. 3
shows spacer sidewalls
60
formed on polysilicon gates
25
after gate oxide
20
has been removed. A third photoresist layer
65
is patterned over N− well region
35
. A masked arsenic N+ implant is performed forming source/drain junctions
70
. Photoresist layer
65
is removed and an annealing thermal cycle is used to drive in the N+ implant.
FIG. 4
shows a fourth photoresist layer
75
patterned into a mask. A masked P+ implant is then performed forming source/drain junctions
80
. Photoresist layer
75
is then removed and an annealing thermal cycle drives in the P+ implant.
Thus, as illustrated in
FIGS. 1-4
, there are four photolithography steps to produce source/drain junctions with LDDs in standard CMOS processing. Each photolithography step, however, is costly and time consuming because of the materials used and the reduction in throughput. Therefore, a method to limit the amount of required photolithography steps is desirable.
SUMMARY
In accordance with the present invention, a low cost method for producing proper source/drain junctions and transistor characteristics for a sub-micron CMOS device uses a minimum of masking steps. Through the consolidation of masking steps, source/drain processing has a significantly lower cost with no performance loss. A blanket P− implant of boron is employed to simultaneously form PLDD junctions for the PMOS and halo regions for the NMOS. After sidewall spacers are formed adjacent to the walls of the gates, a masked arsenic and phosphorous implant is employed as a N+ implant, which is aligned with the sidewall spacers. The arsenic and phosphorous implant overcompensates for the previous boron implant. The NLDD junctions are created during the N+ anneal thermal cycle because the phosphorous drives in under the sidewall spacers faster than the arsenic. The P− halo structure is defined at this time. A masked boron implant is then employed to form the P+ source/drain junctions in the PMOS region.
In an alternative embodiment, phosphorous is not implanted simultaneously with the arsenic, but implanted to form the NLDD junction prior to the sidewall spacer deposition. This alternative embodiment requires the use of a masked implant of the phosphorous.
Thus, two masked implants are used in accordance with one embodiment the present invention to produce the desired source/drain junctions, while three masked implants are used in an alternative embodiment. Consequently, source/drain processing in accordance with the present invention has a significantly lower cost and no performance loss compared to the conventional method, which uses four masks.


REFERENCES:
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5486480 (1996-01-01), Chen
patent: 5534449 (1996-07-01), Dennison et al.
patent: 5654213 (1997-08-01), Choi et al.
patent: 5750424 (1998-05-01), Choi et al.
Stanley Wolf Ph.D., “Silicon Processing for the VLSI ERA vol. 2: Process Integration”, Lattice Press, Sunset Beach, California, pp. 436-437.

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