Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-10
2002-07-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000
Reexamination Certificate
active
06426261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic,circuit and its fabrication method, and more particularly to a circuit structure for implementing a low power consumption CMOS logic circuit.
2. Description of Related Art
A CMOS circuit structure is widely employed in fields such as, mobile telecommunication systems to that consist of low power consumption LSIs with a supply voltage of one volt or less.
FIG. 22
is a circuit diagram showing a conventional CMOS logic circuit. In
FIG. 22
, a CMOS logic circuit C
11
is composed of a high threshold voltage pMOS transistor
81
, a low threshold voltage pMOS transistor
82
, and a low threshold voltage nMOS transistor
83
. In other words, the CMOS logic circuit C
11
is composed of MOS transistors with high threshold voltage and low threshold voltage.
The conventional CMOS logic circuit C
11
has a high operating speed because it uses low threshold voltage MOS transistors
82
and
83
. In addition, smaller leakage current flows through the low threshold voltage MOS transistors
82
and
83
in a sleeping mode than in an operating mode, since the pMOS transistor
81
is kept OFF. This can reduce power consumed by the low threshold voltage MOS transistors
82
and
83
in the sleep mode.
In the CMOS logic circuit C
11
, however, a leakage current flows through the MOS transistors
82
and
83
, since the pMOS transistor
81
is turned on in the operation mode, and the leakage current causes power loss. Thus, the conventional CMOS logic circuit C
11
has a problem in that it cannot prevent a power loss in an operation mode.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a logic circuit capable of reducing the power consumption in the operation mode, while maintaining a high operating speed like the conventional circuit.
It is another object of the present invention to provide a fabrication method for the logic circuit without increasing the process steps.
In a first aspect of the present invention, there is provided a logic circuit comprising:
a first logic gate having at least one first MOS transistor and interposed in a signal path determining an operating speed, the first MOS transistor having a threshold voltage lower than a predetermined voltage and operating at a high-speed; and
one or plural remaining logic gates other than the first logic gate having at least one of a second MOS transistor and a third MOS transistor as a transistor having a margin for operating speed, the second MOS transistor having a medium threshold voltage equal to or greater than the predetermined voltage, and the third MOS transistor having a high threshold voltage equal to or greater than the predetermined voltage.
The logic circuit may further comprise a fourth MOS transistor having a high threshold voltage interposed between a main power supply line and a terminal of at least one of the first and second MOS transistors on the side of a high potential power supply line.
At least one first MOS transistor in the first logic gate may include a fifth MOS transistor constituting a transfer gate interposed in the signal path, and a sixth MOS transistor for controlling the fifth MOS transistor, under one or plural remaining logic gates may include a second logic gate for determining an output of the fifth MOS transistor, and a third logic gate for controlling the sixth MOS transistor.
The sixth MOS transistor may have its drain terminal connected to a gate terminal of the fifth MOS transistor, its source terminal connected to an output terminal of the third logic gate, and its gate terminal connected to one of the high potential power supply line and the main power supply line or the ground.
The first, second and third MOS transistors may have a SOI structure, and at least one of the low threshold voltage first MOS transistor and the medium threshold voltage second MOS transistor may be a fully depleted MOS transistor.
The MOS transistors may have a SOI structure, at least one of the low threshold voltage first MOS transistor and the medium threshold voltage second MOS transistor may be a fully depleted MOS transistor, and the high threshold voltage third MOS transistor may be a fully depleted MOS transistor.
The fifth MOS transistor may be a first first-conductivity-type-channel MOS enhancement transistor having a source connected to a signal input terminal of the transfer gate, and a drain connected to a signal output terminal of the transfer gate, the sixth MOS transistor may be a second first-conductivity-type-channel MOS enhancement transistor having a source connected to an output terminal of the third logic gate, a drain connected to a gate of the first first-conductivity-type-channel MOS enhancement transistor, and a gate connected to the high potential power supply or the ground, and a body of the first first-conductivity-type-channel MOS enhancement transistor and a body of the second first-conductivity-type-channel MOS enhancement transistor may both be made floating.
The first first-conductivity-type-channel MOS enhancement transistor and the second first-conductivity-type-channel MOS enhancement transistor may have a SOI structure.
The first first-conductivity-type-channel MOS enhancement transistor and the second first-conductivity-type-channel MOS enhancement transistor may be of the fully depleted type.
One or plural remaining logic gates may include a full adder for performing addition by receiving first and second input signals and a carry signal, the carry signal being supplied to the transfer gate, the third logic gate may control to determine whether or not the carry signal is output from the transfer gate in response to the first and second input signals, and the second logic gate may generate as an output of the transfer gate an output predetermined in accordance with the first and second input signals when the carry signal is not output from the transfer gate in response to the first and second input signals.
At least one first MOS transistor having a lower threshold voltage may include first and second first-conductivity-type-channel enhancement MOS transistors, the first first-conductivity-type-channel enhancement MOS transistor having a source connected to a signal input terminal, and a drain connected to a signal output terminal; and the second first-conductivity-type-channel enhancement MOS transistor having a source connected to a control terminal, a drain connected to a gate of the first first-conductivity-type-channel enhancement MOS transistor, and a gate connected to a high potential power supply on the ground, the first and second first-conductivity-type-channel enhancement MOS transistors, whose bodies are made floating, may constitute a switching circuit as a transfer gate.
In a second aspect of the present invention, there is provided a fabrication method for fabricating a logic circuit including a first logic gate having at least one first MOS transistor and interposed in a signal path determining an operating speed, the first MOS transistor having a threshold voltage lower than a predetermined voltage and operating at a high speed; and
one or plural remaining logic gates other than the first logic circuit having at least one of a second MOS transistor and a third MOS transistor as a transistor having a margin for operating speed, the second MOS transistor having a medium threshold voltage equal to or greater than the predetermined voltage, and the third MOS transistor having a high threshold voltage equal to or greater than the predetermined voltage,
the fabrication method comprising the steps of:
(A) forming MOS device regions for forming MOS transistors having low, medium and high threshold voltages, the MOS device regions being isolated from each other;
(B) implanting impurity for a low threshold into the MOS device regions for forming the MOS transistors having the low and high threshold voltages; and
(C) implanting impurity for a medium threshold into the MOS device regions for forming the MOS transistors having the medium an
Douseki Takakuni
Fujii Koji
Frank Robert J.
Gluck Jeffrey W.
Niebling John F.
Nippon Telegraph and Telephone Corporation
Venable
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