Localized spacer for a multi-gate transistor

Details Localized spacer for a multi-gate transistor Localized spacer for a multi-gate transistor

2007-03-28

2009-08-18

Toledo, Fernando L (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S157000, C438S164000, C438S197000

Reexamination Certificate

active

07575976

ABSTRACT:
In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.

REFERENCES:
patent: 2003/0013243 (2003-01-01), Doumae
patent: 2007/0048958 (2007-03-01), Liao et al.
patent: 2007/0111454 (2007-05-01), Yeo et al.
patent: 2008/0149984 (2008-06-01), Chang et al.
patent: 2008/0186752 (2008-08-01), Kim
U.S. Appl. No. 11/395,860, filed Mar. 31, 2006, entitled “Stacked Multi-Gate Transistor Design And Method Of Fabrication,” by Brian S. Doyle, et al.
U.S. Appl. No. 11/499,127, filed Aug. 4, 2006, entitled “Double Gate Transistor, Method Of Manufacturing Same, And System Containing Same,” by Ibrahim Ban.
U.S. Appl. No. 11/474,153, filed Jun. 23, 2006, entitled “Double Gate Transistor, Method Of Manufacturing Same, And System Containing Same,” by Ibrahim Ban and Uday Shah.

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