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Block management and replacement method, flash memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Block processing in a block decoding device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Block processing in a maximum a posteriori processor for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Block processing in a maximum a posteriori processor for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Block puncturing for turbo code based incremental redundancy

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Block synchronization detection apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Block-appended checksums

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Blockage aware zero skew clock routing method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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BM/LLR computation for multi-dimensional TCM/BCM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Body bias using scan chains

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boot security using embedded counters

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan cell and methods for integrating and operating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan cell design for high performance I/O cells

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan cell for testing AC coupled line using phase...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan cells to improve testability of core-embedded...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan chain routing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Boundary scan chain with dedicated programmable routing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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