Boundary scan cell design for high performance I/O cells

Details Boundary scan cell design for high performance I/O cells Boundary scan cell design for high performance I/O cells

2000-07-14

2003-05-20

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06567944

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Very Large Scale Integration (VLSI) design. More specifically, the present invention relates to a boundary scan cell design for high performance input/output (I/O) cells.
2. The Background
Microprocessors generally comprise a central processing unit (CPU) on a chip. FIG.
1
. is a block diagram illustrating a typical microprocessor. The core
2
of the chip contains most of the architectural functionality of the microprocessor. The input/output (I/O) logic
8
contains circuitry to interface the core
2
of the chip with the pins
12
of the chip. Lines
6
are connections from the core
2
to the I/O logic
8
and lines
10
are connections from the I/O logic
8
to the pins
12
. Corresponding to each pin of the chip, there is an I/O cell from the I/O logic
8
.
Boundary scan is a collection of design rules applied to integrated circuits that enables testing and debugging of the circuit at the circuit level, at the printed circuit board level, and at the module or system level. IEEE/ANSI Standard 1149.1 is the current industry-wide standard used for rules of boundary scan design.
One component of the boundary scan standard is the boundary scan data register.
FIG. 2
is a schematic diagram illustrating an existing logic design of an output cell that implements one bit of a boundary scan data register. A boundary scan I/O cell
50
has two paths, a functional path and a test path used during boundary scan mode (boundary scan path). The functional path is used for data during the normal operation of the cell. The boundary scan path is used for data during the scan or test mode. Functional flip-flop
52
stores functional data during normal operation. One of ordinary skill in the art will recognize that there are many ways of designing the functional flip-flop within the requirements of the IEEE 1149.1 standard.
These cells are normally arranged all the way around the border of the CPU, hence the name “boundary scan cells”.
Functional flip-flop
52
takes as input data
54
, or d. The output of functional flip-flop
52
is a q line
56
. Functional flip-flop
52
may also be designed to receive clock signal
58
, which controls when data is read out of the storage.
The boundary scan path fans out from the q line
56
and contains two stages, a capture stage
60
and an update stage
62
. Each stage contains a flip-flop. The capture stage is meant for capturing functional data from the q line
56
into the update stage
62
. The capture stage of each of the I/O cells may be chained serially so that captured data can be shifted out serially from the whole boundary scan data register. A clock signal
64
indicates when data should be read out of the capture stage
60
. Boundary scan input signal
66
may be output to the update stage
62
when a shift enable signal
68
is driven high, whereas the input from the q line
56
is output to the update stage
62
when the shift enable signal
68
is low. The update stage flip-flop
62
also has as input an update enable signal
70
which indicates whether or not to update. The output of the boundary scan path is fed to a multiplexor
72
, where it is multiplexed with the functional path, with an boundary scan mode input
74
that indicates whether the functional path or the boundary scan path should be fed to the output of the cell
76
.
Therefore, the functional path runs from functional flip-flop
52
through q line
56
to multiplexor
72
, whereas the boundary scan path runs from functional flip-flop
52
through q line
56
, through capture stage
60
and update stage
62
, and finally to multiplexor
72
.
This cell design may be used as either in input cell or an output cell. In the case of an input cell, the data
54
is tied to a pin at the edge of the chip, while the output of the multiplexor
76
is tied to the interior of the CPU. In an output cell, the data
54
is tied to the interior of the CPU while the output of the multiplexor
76
is tied to a pin at the edge of the chip.
Speed is of critical concern to chip manufacturers. Once the functional flip-flop
52
performs its functions, the speed at which the q output signal
56
reaches a pin (or the interior of the CPU in the case of an input cell) is extremely important. Unfortunately, the presence of multiplexor
72
in the functional path adds a delay which can prove costly. What is needed is a boundary scan cell design which does not suffer this multiplexor delay in a critical path.
SUMMARY OF THE INVENTION
A boundary scan cell design which places the multiplexor before the functional flip-flop on the functional path, reducing the multiplexor delay in the critical path. The re-positioning of the multiplexor is taken advantage of to design an optimal multiplexor and flip-flop combination, allowing for a significant reduction in the time required from the output of the functional flip-flop to a pin or the core of the chip (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.


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