Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-04-01
2008-04-01
Fan, Chieh M. (Department: 2611)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S265000, C714S792000
Reexamination Certificate
active
07353450
ABSTRACT:
A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k−N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2Ninput transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm. During the update process, the read/write operation for an implementation transfers N words of length N for each update operation, but the frequency (and hence, number) of update operations is reduced by a factor of N. Such voltage scaling and multiple word memory read/write may provide reduced power consumption for a given implementation of MAP processor in, for example, a DSP.
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Gabara Thaddeus J.
Lee Inkyu
Lopez-Vallejo Marissa L.
Mujtaba Syed
Agere Systems Inc.
Aghdam Freshteh N
Drucker Kevin M.
Fan Chieh M.
Mendelsohn Steve
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