Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-09-29
1999-11-23
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
39550017, G01R 3128
Patent
active
059919086
ABSTRACT:
A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.
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Baxter Glenn A.
Buch Kiran B.
Law Edwin S.
Pang Raymond C.
Beausoliel, Jr. Robert W.
Cartier Lois D.
Iqbal Nadeem
Xilinx , Inc.
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