Boundary scan apparatus and interconnect test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S724000, C714S726000, C714S718000

Reexamination Certificate

active

07032146

ABSTRACT:
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.

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IBM Technical Disclosure Bulletin. vol. 33. No. 8. Jan. 1991. pp. 82-86. “Chip Interconnect Delay Test and Sort Technique”.

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