Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-09
2002-04-16
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000
Reexamination Certificate
active
06374380
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a boundary scan cell for testing integrated circuits, and more particularly to boundary scan cells improve testability of core-embedded integrated circuits.
BACKGROUND OF THE INVENTION
There are increasing number of core-based integrated circuit (IC) designs lately. It means that a system-on-a-chip (SOC) design style is generally recognized as a new design trend. Thus, a memory core or an analog core, as well as a central processing unit (CPU) core, is frequently used in the IC design. In addition, there is a tendency to invest the IC with plural and various kinds of cores.
In a core-based IC, a testability of a user defined logic (UDL) around the core is dependent upon the accessibility of interface signals between the core and the UDL. The UDL is called a glue logic hereinafter. A direct access (DA) testing method, extracting these interface signals to external pins, is simple and effective. The DA testing method is set forth in a paper titled “Direct Access Test Scheme-Design of Block and Core Cells for Embedded ASIC”, by V. Immaneni and S. Raman, Proc. of International Test Conference, pp. 488-492, 1990. In that case, if the number of interface signals is high, it is hard to test the core-embedded circuit due to excessive pin overhead.
One proposed solution to the foregoing problem involves constructing an isolation ring around the core, which is generally used for testing the core and the glue logic. The method is described in a paper titled “Modifying User-Defined Logic For Test Access To Embedded Cores,” by B. Pouya and N. A. Touba of International Test Conference, pp. 60-68, 1977. According to that testing method, each block embedded in the IC can be tested separately by constructing a boundary scan chain between the core and the glue logic, so that all the interface signals to the cores become fully accessible and the testability of the core and the glue logic can be improved without an excessive pin overhead. For this purpose, well-known Joint Test Action Group (JTAG) boundary scan design method, IEEE standard 1149.1 may be adopted.
However, the JTAG method requires not only additional logic overhead of a test access port (TAP) controller but also compliance to the complex test protocols of the standard. For more detailed description of the boundary scan test technique embedded in the IEEE standard 1149.1, reference should be made to the publication IEEE standard TAP and boundary scan architecture, published by the Institute of Electrical and Electronics Engineers, New York (1990), herein incorporated by reference.
Other examples of boundary cells are disclosed in U.S. Pat. No. 5,220,281 to Matsuki, issued on Jun. 15, 1993, “BOUNDARY SCAN CELL FOR Bidirectional INPUT/OUTPUT TERMINALS”; U.S. Pat. No. 5,260,948 to Simpson et al., issued on Nov. 9, 1993, “BIDIRECTIONAL BOUNDARY SCAN CIRCUIT”; and U.S. Pat. No. 5,701,307 to Lee D. Whetsel, issued on Dec. 23, 1997, “LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS”, all of which disclosures are incorporated herein by reference. However, an unavoidably excessive constructional pin overhead is generated in the above boundary scan cells adopting the IEEE standard 1149.1.
For this reason, it may be difficult to test the core and the glue logic with a lower pin overhead and an improved testability. Therefore, a new boundary scan cells design is needed to increase the testability of the core and the glue logic, respectively or together, with minimal area overhead and simple test control, compared to the JTAG method.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide boundary scan cells increasing the testability of the core and the glue logic, respectively or together, with minimal area overhead and simple test control.
In order to attain the above objects, according to an aspect of the present invention, there is provided a core-embedded integrated circuit comprising a first logic block, a second logic block, a signal line coupled between the first logic block and the second logic block for inputting/outputting an input/output signal of the logic blocks, and a boundary scan cell coupled to the signal line for loading/capturing the input/output signal for testing the first logic block and the second logic block, respectively or together, with minimum overhead. The boundary scan cell is adapted for serial connection with other similar boundary scan cells in a single chain and each scan cell has a data holding capability for data loading.
In the core-embedded circuit according to the invention, the boundary scan cell comprises: a scan flip-flop having a plurality of input ports receiving plural corresponding data input signals, a scan input signal, a scan enable signal and a scan clock signal, and an output port, so as to perform a scan operation for generating a scan output signal, and a normal operation for capturing the bidirectional signal or loading the scan output signal into one of the logic blocks through the bidirectional signal line; a first multiplexer for generating the data input signal of the scan flip-flop by selecting either the bidirectional signal from the bidirectional signal line or the scan output signal from the scan flip-flop, to perform the normal operation, in response to an input/output control signal determining an input/output direction of the scan cell; a logic circuit for generating a load control signal in response to the scan enable signal enabling the scan operation, the first mode control signal enabling the test operation, and the input/output control signal determining the direction of the scan cell; and a tri-state buffer for loading the scan output signal to one of the logic blocks through the bidirectional signal line in response to the load control signal.
REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5452239 (1995-09-01), Dai et al.
patent: 5843799 (1998-12-01), Hsu et al.
patent: 5960191 (1999-09-01), Sample et al.
Amanze Emeka J.
De'cady Albert
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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