Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-12-04
2007-12-04
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000, C714S731000
Reexamination Certificate
active
10762799
ABSTRACT:
An apparatus for performing a boundary scan test is provided, along with method for integrating and operating the same. The apparatus includes an asynchronous flip-flop that has a data input, a data output, a system clock input, a set input, and a reset input. The apparatus also includes a test controller that has a test clock input, a first test data output, and a second test data output. The first test data output of the test controller is connected to the set input of the asynchronous flip-flop. In addition, the second test data output of the test controller is connected to the reset input of the asynchronous flip-flop. The test controller is configured to control the asynchronous flip-flop through the set input and the reset input. The apparatus for performing the boundary scan test avoids introduction of adverse delay and skew effects caused by multiplexing circuitry.
REFERENCES:
patent: 5574731 (1996-11-01), Qureshi
patent: 6393592 (2002-05-01), Peeters et al.
patent: 6813739 (2004-11-01), Grannis, III
patent: 2004/0268181 (2004-12-01), Wang et al.
Adaptec, Inc.
Britt Cynthia
Martine & Penilla & Gencarella LLP
Siddiqui Saqib
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