Boundary scan apparatus and interconnect test method

Details Boundary scan apparatus and interconnect test method Boundary scan apparatus and interconnect test method

2006-01-19

2008-09-23

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07428677

ABSTRACT:
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.

REFERENCES:
patent: 5127008 (1992-06-01), Bassett et al.
patent: 5150366 (1992-09-01), Bardell et al.
patent: 6260163 (2001-07-01), Lacroix et al.
patent: 6335894 (2002-01-01), Iwata et al.
patent: 6369632 (2002-04-01), Barnes
LSSD Scan Path Truncated to Minimum Length for Testing (IBM Technical Disclosure Bulletin NM83056547, May 1983, vol. # 25).

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