Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-04-05
2005-04-05
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06877121
ABSTRACT:
An apparatus and a method for testing Alternating Current (AC) coupled interconnects of a circuit using boundary scan methodology are disclosed. A Boundary Scan Cell (BSC) of a transmitting Integrated Circuit (IC) generates an AC signal based on a value of the BSC of the transmitting IC and a reference clock. A Sync Pulse cell at the receiving IC generates a sync pulse signal to the BSC of the receiving IC. The BSC of the receiving IC captures a default phase of the AC signal in relation to the sync pulse signal and also captures a phase of a source of input signal. The BSC of the receiving IC then compares the phase of a source of input signal with the phase of said AC signal in relation to the phase captured at the snyc pulse signal and sends out an output signal based on the comparison.
REFERENCES:
patent: 5444715 (1995-08-01), Gruetzner et al.
patent: 6199182 (2001-03-01), Whetsel
patent: 6286119 (2001-09-01), Wu et al.
patent: 6606575 (2003-08-01), Miller
Harisharan Udupi
Ramaswamy Chidambaram
Srinivasaiah Chandrasekhar Thyamagondlu
Abraham Esaw
Cisco Technology Inc.
DeCady Albert
Ritchie David B.
Thelen Reid & Priest LLP
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