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Apparatus, system, and method for hard disk drive redundancy

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatuses and methods for checking integrity of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Application of a Meta-Viterbi algorithm for communication...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Application of a Meta-Viterbi algorithm for communication...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Application of special ECC matrix for solving stuck bit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Application specific distributed test engine architecture...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Application specific integrated circuit with internal testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Application specified integrated circuit with user programmable

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Application-specific integrated circuit (ASIC) for use in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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ARA type protograph codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture and control of reed-solomon error-correction...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture and control of reed-solomon list decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture and method for testing of an integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture for a message bus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture for an iterative decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture for built-in self-test of parallel optical...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture for soft decision decoding of linear block...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Architecture of an efficient at-speed programmable memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Architecture, circuitry and method for testing one or more...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Area efficient BIST system for memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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