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Universal parity encoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Updating and reading data and parity blocks in a shared disk sys

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Updating and reading data and parity blocks in a shared disk...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Updating high speed parallel I/O interfaces based on counters

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Usage of an SDRAM as storage for correction and track...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Usage of an SDRAM as storage for correction and track...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Usage of redundancy data for displaying failure bit maps for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Use of a scan chain for configuration of BIST unit operation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Use of ECC with iterative decoding for iterative and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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User available body scan chain

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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User equipment using hybrid automatic repeat request

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Using bit errors from memory to alter memory command stream

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Using clock gating or signal gating to partition a device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Using data compression for faster testing of embedded memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Using error checking bits to communicated an address or...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Using hardware or firmware for cache tag and data ECC soft...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Using microcode to correct ECC errors in a processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Using profiles to perform Bit Error Rate Testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Patent

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Using profiles to perform bit error rate testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Using quadrant shifting to facilitate binary arithmetic with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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