Universal parity encoder

Details Universal parity encoder Universal parity encoder

2008-06-24

2008-06-24

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S701000

Reexamination Certificate

active

07392464

ABSTRACT:
A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

REFERENCES:
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patent: 6456208 (2002-09-01), Nazari et al.
patent: 6631490 (2003-10-01), Shimoda
patent: 6795947 (2004-09-01), Siegel et al.
U.S. Appl. No. 10/715,551, filed Nov. 17, 2003, Feng, Weishi.
U.S. Appl. No. 10/714,804, filed Nov. 17, 2003, Feng, Weishi.
U.S. Appl. No. 10/639,796, filed Aug. 12, 2003, Feng, Weishi et al.
U.S. Appl. No. 10/423,552, filed Apr. 25, 2003, Feng, Weishi et al.

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