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Selecting between tap/scan with instructions and lock out...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selecting different 1149.1 TAP domains from update-IR state

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selecting K in a data transmission carousel using (N,K)...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Selecting test circuitry from header signals on power lead

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selection of status data from synchronous redundant devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Selective bit error detection at a bus device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Selective control of test-access ports in integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selective control of test-access ports in integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selective packet retransmission with timing control at the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Selective scrambler for use in a communication system and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Selectively accessing test access ports in a multiple test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Selectively debugging processor cores through instruction codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self learning signatures

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self orthogonal decoding circuit and self orthogonal...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Self programmable shared bist for testing multiple memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self resetting high speed redundancy circuit and method thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Self synchronous scrambler apparatus and method for use in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Self test apparatus for identifying partially defective memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Self test circuit for a semiconductor intergrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Self test device and self test method for reconfigurable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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