Selective bit error detection at a bus device

Details Selective bit error detection at a bus device Selective bit error detection at a bus device

2006-04-24

2009-12-08

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S704000

Reexamination Certificate

active

07631229

ABSTRACT:
In one aspect, a data transmission rate of a message signal representing a bus message at a bus and a propagation delay between an occurrence of the message signal at a transmission output to the bus and an occurrence of the message signal at a receive input from the bus are determined. Bit error detection is selectively disabled responsive to a compatibility between the data transmission rate and the propagation delay. In another aspect, a bus line interface includes a transmit output and a receive input coupled to a bus line, a bit error detection module and a data rate module. The bus line interface also includes a bit error control module to selectively disable the bit error detection module based on a propagation delay between a signal and a reflected signal and based on a data transmission rate of the signal.

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