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System and methods of balancing scan chains and inserting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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System and process for delivering digital data on demand

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System and scanout circuits with error resilience circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System and shadow circuits with output joining circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System architecture for internet telephone

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System configuration and methods for on-the-fly testing of integ

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System correcting random and/or burst errors using RS...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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System correcting random and/or burst errors using RS...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System debugging device and system debugging method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System decoder having error correcting memories for high-speed d

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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System for analyzing a failure in a semiconductor wafer by calcu

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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System for at-speed automated testing of high serial pin...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for at-speed automated testing of high serial pin...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for changing the parity structure of a raid array

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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System for coding system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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System for computing a CRC value by processing a data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System for correcting errors in data frames having horizontal an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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System for decoding coded data with PLL

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System for dynamic re-allocation of test pattern data for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for efficient utilization of multiple test systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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