Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-12
2007-06-12
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C709S240000
Reexamination Certificate
active
10975397
ABSTRACT:
A system debugging device in which, even if bus ownership is transferred to other bus masters, the operations of the other bus masters can be monitored such that efficient debugging of a system can be achieved is provided. In a system where a plurality of bus masters mounted on an LSI share a bus, the system debugging device includes a recorder for recording a variety of information including master selection information for specifying a bus master to which a right to use the bus is granted and slave selection information for selecting a bus slave specified according to address signals outputted from the bus master; and a reader for reading, via the bus, the variety of information recorded in the recorder.
REFERENCES:
patent: 5159263 (1992-10-01), Yaguchi
patent: 5525971 (1996-06-01), Flynn
patent: 5636342 (1997-06-01), Jeffries
patent: 6463488 (2002-10-01), San Juan
Kawasaki Microelectronics Inc.
Oliff & Berridg,e PLC
Tu Christine T.
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