System and scanout circuits with error resilience circuit

Details System and scanout circuits with error resilience circuit System and scanout circuits with error resilience circuit

2007-10-02

2007-10-02

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S703000

Reexamination Certificate

active

11050996

ABSTRACT:
In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.

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Mitra et al., “Robust System Design with Built-In Soft-Error Resilience,” IEEE Computer Society, Feb. 2005, XP-002378078, pp. 43-52.

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