Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1996-01-18
2000-04-25
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060556617
ABSTRACT:
An integrated circuit (IC) testing system is provided by the present invention. The IC testing system is for testing a device under test (DUT) IC. The IC testing system includes an interface to a target system. The target system incorporates a known good IC (KGIC) which is identical to the DUT. The KGIC is implemented on the target system as it is designed to be used during the normal operation of the target system. The target system will then exercise the KGIC by running the diagnostic programs or by sending appropriate instructions or commands to invoke the KGIC to perform different functions for the target system. The interface system provided by the present invention for performing an IC test will then capture the signals to and from the KGIC on-the-fly. The testing system of the present invention will redirect the KGIC input signals to the DUT as testing input signals, i.e., input stimuli. The output signals generated by the will be used as the reference signals for comparison with the corresponding response signals from the DUT for fault detection.
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Cady Albert De
Chase Shelly A
Lin Bo-In
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