System and methods of balancing scan chains and inserting...

Details System and methods of balancing scan chains and inserting... System and methods of balancing scan chains and inserting...

2007-05-15

2010-10-26

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000, C716S030000

Reexamination Certificate

active

07823035

ABSTRACT:
A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip-level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.

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“Optimal configuring of multiple scan chains” by Narayanan et al. This paper appears in: Computers, IEEE Transactions on Publication Date: Sep. 1993 vol. 42, Issue: 9 On pp. 1121-1131 ISSN: 0018-9340 INSPEC Accession No. 4580572.
International Search Report and Written Opinion for International Application No. PCT/US08/61526.

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