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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing random-access memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing semiconductor apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Method of testing the data exchange functionality of a memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of the ARQ type for a transmission method using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method of transmitting digital data packets and device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method of transmitting ethernet frame in network bridge and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method of transmitting signaling messages in a mobile...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method of updating an associative memory of the TRIE type,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of using link adaptation and power control for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Method on scan chain reordering for lowering VLSI power...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method relating to processors, and processors adapted to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method system and program products for error correction code...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method tester and circuit for applying a pulse trigger to a unit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to descramble the data mapping in memory circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to determine retries for parallel ECC correction in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method to locate logic errors and defects in digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to obtain the worst case transmit data and jitter...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Method to prevent inadvertent test mode entry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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