Hardware-efficient CRC generator for high speed...
Hardware-efficient low density parity check code for digital...
Hardware-efficient low density parity check code for digital...
HARQ method for guaranteeing QoS in a wireless communication...
HARQ transmission feedback for higher layer protocols in a...
Hashing system utilizing error correction coding techniques
Head degradation characterization for a data storage device
Header compressed packet receiving apparatus and method
Header-formatted defective sector management system
Hidden failure detection
Hierarchical access of test access ports in embedded core...
Hierarchical block coding for a packet-based communications...
Hierarchical built-in self-test for system-on-chip design
Hierarchical creation of vectors for quiescent current...
Hierarchical design and layout optimizations for high...
Hierarchical test access port architecture for electronic...
Hierarchical test circuit structure for chips with multiple...
Hierarchical test response compaction for a plurality of...
Hierarchical trellis coded modulation
Hierarchically-controlled automatic test pattern generation