Hierarchical design and layout optimizations for high...

Details Hierarchical design and layout optimizations for high... Hierarchical design and layout optimizations for high...

2004-11-10

2009-11-10

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S804000

Reexamination Certificate

active

07617432

ABSTRACT:
High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.

REFERENCES:
patent: 6938196 (2005-08-01), Richardson et al.
patent: 7376885 (2008-05-01), Richardson et al.

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