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ECC for single 4-bits symbol correction of 32 symbols words...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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ECC for single 4-bits symbol correction of 32 symbols words...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ECC functional block placement in a multi-channel mass...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ECC in memory arrays having subsequent insertion of content

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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ECC Q-parity checkbyte indexing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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ECC scheme for wireless digital audio signal transmission

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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ECC system employing a data buffer for storing codeword data and

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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ECC system for generating a CRC syndrome over randomized data in

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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ECC with out of order completion

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Echo canceler-based mechanism for performing and reporting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Echo canceler-based mechanism for performing and reporting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Edge incremental redundancy memory structure and memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Edge selecting triggering circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Edge-triggered master + LSSD slave binary latch

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Edge-triggered scan flip-flop and one-pass scan synthesis...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Editing apparatus and generating method for physical...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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EEPROM memory including an error correction system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Efficient address generation for interleaver and de-interleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Efficient air-flow loop through dual burn-in chambers with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Efficient almost regular permutation (ARP) interleaver and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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