ECC for single 4-bits symbol correction of 32 symbols words...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07996748

ABSTRACT:
An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.

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D. Rossi, et al., “Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories”, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002).
C.L. Chen, “Symbol Error-Correcting Codes for Computer Memory Systems”, IEEE Transactions on Computers, vol. 41, No. 2, Feb. 1992.
Lin, Costello, “Error Control Coding” 2004, Pearson Prentice Hall, USA, pp. 920-921.

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