Efficient address generation for interleaver and de-interleaver

Details Efficient address generation for interleaver and de-interleaver Efficient address generation for interleaver and de-interleaver

2006-04-04

2006-04-04

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S786000

Reexamination Certificate

active

07024596

ABSTRACT:
Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving. The present invention also provides for reading, writing, and updating offset registers in a code word by code word base manner.

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