Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-03-15
2002-03-19
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000
Reexamination Certificate
active
06360341
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an editing apparatus and a generating method for physical conversion definition for generating physical conversion definition for converting a physical address of a memory cell in semiconductor memory into a logical address and an I/O number.
A semiconductor memory test system is a system to analyze a failure of each memory cell in semiconductor memory (hereinafter, this is simply called memory) by reading data from or writing data to each memory cell. In general, a semiconductor memory test system, as shown in
FIG. 43
, comprises a timing generator
110
, a pattern generator
112
, a waveform shaper
114
, a logical comparator
116
, and fail memory
118
. An address and data generated by the pattern generator
112
are inputted to memory under test (MUT) after waveform-shaping by the waveform shaper
114
. The logical comparator
116
compares data read from the MUT with an expected value outputted from the pattern generator
112
, and judges pass or fail. The fail memory
118
saves fail information every address from a fail signal outputted from the logical comparator
116
and an address signal outputted from the pattern generator
112
. A series of these operations are synchronized with a system clock inputted from the timing generator
110
into each unit.
In this manner, data relating to pass or fail of each memory cell of the MUT is saved in the fail memory
118
included in the semiconductor memory test system. Furthermore, failure analysis of the memory is performed by collecting the data and surveying contents of the data by a host system and the like.
By the way, physical arrangement of actual memory cells may be frequently different from address information inputted into memory (logical address). Therefore, even if the fail information saved in the fail memory
118
, described above, is read, it is unknown which memory cell is defective.
A map showing a memory address where a failure is detected is called a “fail bit map.” A fail bit map is separated into a logical fail bit map and a physical fail bit map. The logical fail bit map is a four-dimensional fail bit map where logical addresses X, Y, and Z, and an I/O number are used as coordinates, and becomes a three-dimensional map in case the logical address Z is not used. This logical fail bit map can be obtained on the basis of fail information read from the fail memory
118
described above. The physical fail bit map is a two-dimensional fail bit map where physical addresses X and Y are used as coordinates, and is used when physical arrangement of a defective memory cell of the memory is confirmed. Since the failure analysis of the memory is usually performed with using this physical fail bit map, it becomes necessary to convert a logical fail bit map obtained by the fail memory
118
into a physical fail bit map.
In general, conversion of a logical fail bit map into a physical fail bit map is called “physical conversion.” In a broad sense, it is called physical conversion to obtain a two-dimensional fail bit map with using a logical fail bit map and a physical conversion definition. Here, physical conversion definition means information for performing the physical conversion, the information which includes information for rapidly obtaining logical addresses and an I/O number from a physical address.
The physical conversion definition described above is performed with using an editing apparatus for physical conversion definition. Hereinafter, a generating method for physical conversion definition with using a conventional editing apparatus for physical conversion definition will be described.
(1) Setting of Address Parameters'
First, various address parameters are set. Concretely, the following parameters are set:
Size of horizontal logical address: HL
Size of vertical logical address: VL
I/O size: IO
Size of horizontal physical address: HP
Size of vertical physical address: VP
Axes of address
Here, respective values are set so that formula HL×VL×IO=HP×VP may hold. For example, HL=32, VL=16, IO=4, HP=64, and VP=32 are set, and the X-axis is set in the horizontal direction and the Y-axis is set in the vertical direction.
(2) Generation of Unit Layout
Next, a unit layout will be generated. This unit layout has three kinds of information, that is, width, height, and a position of an origin. Although a plurality of units whose sizes are different from each other are allowed, unit layouts besides a basic unit layout that is smallest are integer times as large as the basic unit layout.
FIGS. 44A and 44B
are diagrams showing concrete examples of the unit layout. As for a unit layout “a” shown in
FIG. 44A
, width is set at 24, height is at 4, and an origin is set on the upper right. In addition, as for a unit layout “b” shown in
FIG. 44B
, width is set at 8, height is at 4, and the origin is on the upper left.
(3) Generation of Block Layout
Next, a block layout is generated. The block layout is a layout where a plurality of units is arranged in a grid-like pattern, and a unit layout and an I/O number are assigned to each unit. It is not necessary that sizes of units included in a block are uniform so long as height or width of each row or each column is uniform.
FIGS. 45A and 45B
are diagrams showing concrete examples of the block layout. A block layout A shown in
FIG. 45A
is set at 2 columns and 4 rows, and is composed by combining the unit layout “a,” shown in
FIG. 44A
, with the unit layout b, shown in
FIG. 44B
, in the horizontal direction and alternately combining unit layouts, which have I/O numbers
0
and
1
, in the vertical direction. Therefore, the width of the block layout A is set at 32 and the height is at 16. Similarly, the width of a block layout B shown in
FIG. 45B
is set at 2 columns and 4 rows, and is composed by combining the unit layout “a”, shown in
FIG. 44A
, with the unit layout “b”, shown in
FIG. 44B
, in the horizontal direction and alternately combining unit layouts, which have I/O numbers
2
and
3
, in the vertical direction. Therefore, the width of the block layout B is set at 32 and the height is at 16.
(4) Generation of Main Layout
Next, a main layout is generated. The main layout is a layout where a plurality of blocks is arranged in a grid-like pattern, and a block layout and a sequence number are assigned to each block. Since sequence is meaningful for the sequence number, repeated numbers are not allowable. Block layouts assigned to blocks should have the same numbers of units in the horizontal direction and also in the vertical directions respectively, and furthermore, should have same numbers of memory cells in the horizontal direction and also in the vertical directions respectively.
FIG. 46
is a diagram showing a concrete example of a main layout. In the main layout shown in
FIG. 46
, respective block numbers in the horizontal and vertical directions are set at 2, and the main layout is composed of combining the block layouts A and B with the block layouts B and A. In addition, the sequence number “1” is set to the block layout A on the upper left, “4” is to the block layout A on the lower right, “7” is to the block layout B on the upper right, and “9” is to the block layout B on the lower left.
(5) Setting of Priority Direction in Address Assignment
Subsequently, either the horizontal direction or the vertical direction is set as the priority direction in address assignment.
After terminating the definition work by above operations (1) through (5), logical addresses X and Y are automatically assigned according to the following rules:
The origin of a physical address should be always on the upper left.
If the horizontal direction is X and the vertical direction is Y, the horizontal direction should be X and the vertical direction should be Y also in a physical address and a logical address. On the contrary, if the horizontal direction is Y and the vertical direction is X, the horizontal direction should be Y and the vertical direction shoul
Advantest Corporation
Chung Phung M.
Dellett and Walters
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