Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-12-03
1999-12-28
Baker, Stephen M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
395872, 714773, G11C 2900
Patent
active
060095474
ABSTRACT:
Disclosed is a memory array system, such as a DRAM, for the temporary storage of data. ECC check symbols for insuring the correctness of the data are written to a different segment of the memory array from the data. The data is formatted into blocks of length (l), directly related to the standard sized access width of the memory array, and gap blocks of length (l) are inserted into the data stream for subsequent substitution of headers. The data and associated headers may have appended check symbols calculated with a Reed-Solomon generator polynomial. The data blocks are written into memory partitions with an exact alignment of blocks with partition boundaries, so that no gap block spans a partition boundary. ECC encoding logic calculates the ECC check symbols, employing an identical Reed-Solomon generator polynomial for each partition. The headers with the associated CRC are subsequently substituted for the gap blocks. By use of identical polynomials in the headers and the ECC covering the partitions, and by having the system insure that no gap (left for a header to be written later) spans a partition boundary, no net contribution to the ECC is made by the first Reed-Solomon check symbols.
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Jaquette Glen Alan
Washburn Gordon Leon
Baker Stephen M.
Holcombe John H.
International Business Machines - Corporation
Sullivan Robert M.
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