Configuration for generating signal impulses of defined...

Configuration for testing an integrated semiconductor memory...

Configuration of memory cells and method of checking the...

Configurator arrangement and approach therefor

Configuring flash memory

Connecting analog response to separate strobed comparator...

Connecting multiple test access port controllers on a single...

Connection matrix for a microcontroller emulation chip

Connection of auxiliary circuitry to tap and instruction...

Connection of auxiliary circuitry to tap and instruction...

Connection verification apparatus for verifying...

Construction and use of shortened EG-LDPC codes

Construction of an optimized SEC-DED code and logic for soft...

Construction of irregular LDPC (low density parity check)...

Content addressable memory having reduced power consumption

Content addressable memory match line detection

Content addressable memory with error detection

Content addressable memory with error signaling

Content addressable memory with priority-biased error...

Content and channel aware object scheduling and error control