Content addressable memory with priority-biased error...

Details Content addressable memory with priority-biased error... Content addressable memory with priority-biased error...

2006-05-09

2006-05-09

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07043673

ABSTRACT:
A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

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