Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-03
2006-10-03
Torres, Joseph (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S773000
Reexamination Certificate
active
07117420
ABSTRACT:
An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.
REFERENCES:
patent: 3623155 (1971-11-01), Hsiao et al.
patent: 4464753 (1984-08-01), Chen
patent: 4486882 (1984-12-01), Piret et al.
patent: 4726021 (1988-02-01), Horiguchi et al.
patent: 4730320 (1988-03-01), Hidaka et al.
patent: 4736376 (1988-04-01), Stiffler
patent: 5233614 (1993-08-01), Singh
patent: 5535227 (1996-07-01), Silvano
patent: 5600659 (1997-02-01), Chen
patent: 5719887 (1998-02-01), Kazuno
patent: 5841795 (1998-11-01), Olarig et al.
patent: 5856987 (1999-01-01), Holman
patent: 5922080 (1999-07-01), Olarig
patent: 6233717 (2001-05-01), Choi
patent: 2002/0041647 (2002-04-01), Lin et al.
Stephen B. Wicker, Error Control for Digital Communication and Storage, Prentice-Hall 1995; pp.99-121.
Hsiao, M.Y., “A Class of Optimal Minimum Odd-weight-column SEC—DED Codes”,IBM Journal of Research and Development, vol. 14, No. 4, Jul. 1970, pp. 394-401.
Book: Siewiorek, Daniel P., and Swarz, Robert S.,Reliable Computer Systems Design and Evaluation, Third Ed.,AK Peters, 1998, pp. 771-777.
Book: Adamek, Jiri,Foundation of Coding: Theory and Applications of Error-Correcting Codes,John Wiley & Sons, Inc., 1991, pp. 48-51, 63-75, and 114-125.
Stephani Richard J.
Vilchis Miguel A.
Yeung Max M.
Christopher P. Maiorana P.C.
LSI Logic Corporation
Torres Joseph
LandOfFree
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